资源列表
chengfaqi
- verilog语言编写的一个乘法器程序，是16位相乘！已通过仿真，用Quartus II 9.1 编写-a multiplier verilog language program, is 16 multiplied by! Through simulation, the Quartus II 9.1 to write
vga
- verilog语言编写的一个vga程序，是vga显示程序，用Quartus II 9.1 编写-a vga verilog language program is a vga display program, the Quartus II 9.1 to write
lcd
- verilog语言编写的一个lcd控制程序，是lcd显示程序，用Quartus II 9.1 编写-verilog language lcd control procedures, lcd display program written using the Quartus II 9.1
NIOS-II
- nios ii中文教程 可编程软核处理器-nios ii Chinese tutorial programmable soft-core processor
klc_iic
- 基于I2C接口的的从机verilog代码，带子地址的发送方式，已下FPGA板子调通，大家可以借鉴。-Based on the I2C interface of the Verilog code, the tape address to send the next FPGA board tune pass, we can learn from.
elec_clock_if
- VHDL 最简单数字电子时钟程序（一个process），无时间设置，闹钟等功能。-VHDL simple digital electronic clock program (ONLY a process). NO the time setting, alarm clock function.
fre_counter
- 基于FPGA的频率计，超简洁，再测fx=10 KHz的方波时，得到的频率是9.995 KHz ，误差为0.05-Frequency Meter based on FPGA
VHDL-counter
- 在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。我们知道，在硬件电路设计中时钟信号时非常重要的。 下面我们介绍分频器的VHDL描述，在源代码中完成对时钟信号CLK的2分频，4分频，8分频，16分频。 -In digital circuits, and often need high frequency clock divider operating in lower frequency clock signal. We know that when the c
bert
- 误码测试仪，基于FPGA的E1口误码测试仪-BER tester, based on FPGA-E1 port BER tester
Div_Fre
- 5分频器，功能是对需要信号进行五分频，生成周期为原来五倍的信号-5 divider, the fifth of the frequency on the need to signal the build cycle for the original five times the signal
decode38a
- 3-8译码器的输入是3个脚,输出是8个脚。用高低电平来表示输入和输出。输入是二进制。3只脚也就是3位二进制数。-3-8 decoder input is 3 feet, and the output is 8 feet. High and low input and output. Input is binary. 3 feet 3 binary number.
led
- LED 它的基本结构是一块电致发光的半导体材料，置于一个有引线的架子上，然后四周用环氧树脂密封，起到保护内部芯线的作用，所以 LED 的抗震性能好。 -The basic structure of the LED it is an electric semiconductor materials, placed on a wire rack, four weeks and then sealed with epoxy resin, played the role to protect the