资源列表
dds-5
- 基于FPGA cyclone III EP3C16F484C6的dds正弦波发生器，频率可调-the dds sine wave generator based on the FPGA cyclone III EP3C16F484C6 , frequency adjustable
fsm
- FSM状态机例子，可以给初学者参考学习使用-FSM State machine example, can give the reference for beginners learning to use
Verilog_div_frequency
- 本文使用实例描述了在 FPGA/CPLD 上使用 Verilog进行分频器设计，主要包括50 占空比的奇数分频. -This article uses the example describes the crossover design using Verilog in FPGA/CPLD, including the 50 duty cycle odd divider
MC8051
- FPGA的8051 IP核，完整的工程，直接用Keil编写好单片机代码后将生成的HEX文件放进FPGA的ROM里面，便可使用，比51单片机速度更快！-FPGA-8051 IP core, the complete works directly with Keil to write a good microcontroller code will be generated HEX file into the FPGA-ROM which can be used faster than the sp
IRDATA
- FPGA接收红外线，Verilog代码，完整的工程-FPGA to receive infrared, Verilog code, complete the project
VIP_scaler
- FPGA处理图像缩放的工程模块，是在Quartus II里面调用VIP中的Scaler IP核做的-FPGA processing project module, image scaling is done in the Quartus II which calls VIP Scaler IP Core
sdram_mdl
- FPGA控制SDRAM的工程，是用Verilog写的，很好用-FPGA to control the SDRAM project is written in Verilog, easy to use
and2
- and on vhdl code source .
bascul
- bascule_D on vhdl code source .
compteur
- compteur on vhdl code source .
VHDL
- vhdl 分频程序 简单 方便使用-the vhdl sub-frequency program is simple and easy to use
fsm
- verilog finite state machine program