资源列表
UART
- 用VHDL编写实现的UART控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the VHDL source code to achieve the UART controller, bring their own testbench, after decompression project file can be opened with the ISE.
Altera-Ball-Bouncing-Control.tar
- Altera DE2 Board VGA Ball bouncing Control
multiplexer
- multiplexer unit designed in vhdl VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Descr iption Language.
chengxu
- 信号测量 实时显示 延时2秒 键盘扫描
jianpan
- 设计出4*4矩阵键盘对某一按键按下就在数码管显示一个数字。按键从左上角到右下角依次为1，2，…，16。-Design a 4* 4 matrix keyboard press of a button on the digital display a number. Order from left to bottom right button 1, 2, ..., 16.
DE0_NANO_ADC
- Altera DE0-Nano 开发平台ADC模数转换应用官方DEMO。-Altera DE0-Nano development platform ADC analog-to-digital conversion applications official the DEMO.
adaptive_lms_equalizer_latest.tar
- It is the code for Adaptive Equalizer LMS Algorithm-It is the code for Adaptive Equalizer LMS Algorithm..!!
calender
- 这是用Verilog语言编写的万年历源代码，其中以小时为最小单位，可以区分闰年。有瑕疵还望海涵。-This is the calendar source code written in Verilog language, which hour is the smallest unit that can differentiate between leap years.
adaptive_lms_equalizer_latest.tar
- least mean square algorithm for error correction coding technique
朱明辉vhdl大作业
- 一个双向总线的vhdl实现-a two-way bus VHDL achieve
key
- FPGA按键扫描通用程序，使用时修改一个参数即可，使用modelsim开发环境-FPGA keyboard scanning procedures, when used to modify a parameter, use the Modelsim development environment
cores
- a core has been developed for your 32 bit fpu with a least 32x2 input 4 bit operator with round off and 32 bit output and 8 bit exeption data.