资源列表
Binary_to_BCD_Converter
- General Binary-to-BCD Converter The linked code is a general binary-to-BCD Verilog module, and I have personally tested the code.
Interleaver
- 自己做的交织器，里面包含了交织器的源程序，和交织器的仿真电路文件等等。。。调试后，实现结果正确-Do their own interleaver, which contains the source code interleaver and interleaver circuit simulation files and so on. . . After commissioning, to achieve the right results
imageprocess
- 典型的图像采集verilog代码，开发板源码-this is typical image process code,provided by xilinx developmentpacadge
arm10_verilog
- arm10_verilog.rar是基于arm10的verilog代码，对学习和理解 arm10的工作原理和做基于verilog的FPGA开发有帮助。
sipo
- shifter unit designed in vhdl VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Descr iption Language.
3-8Decoder
- 二进制译码器只显示0，1。十进制译码器显示0-9、显示译码器显示0—F-Show only 0,1 binary decoder. Showing 0-9 decimal decoder, display decoder display 0-F
ipv4_packet_transmitter_latest.tar
- VHDL ethernet implementation on a FPGA
flipflop
- flip flop unit designed in vhdl VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Descr iption Language.
ACtel-RTC-hdl
- 基于Actel公司的反熔丝FPGA实现，实现了实时时钟功能。能区分闰年、大月、小月，秒、分、时自动增长。-this application provides a count of seconds, minutes, hours, day of the week, day of the month, month, and year. The month-ending date is automatically adjusted for months with less than
Servo-using-the-program
- 本文是用AVR atmega8语言写的一个控制舵机的例子，用单片机脉冲PWM信号控制舵机角度，抖动小。-This article is written in the language with AVR atmega8 example of a servo control, PWM signal with a single-chip pulse control steering angle jitter.
andgate
- and gate unit designed in vhdl VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Descr iption Language.
verilog_multiplier
- verilog实现16*16位乘法器，带测试文件-verilog achieve 16 * 16 multiplier, with test documents