资源列表
6_Sets_of_8051_VHDL_Verilog
- it has 6 packages of 8051 sources,including source code(VHDL and Verilog),dc scr ipts, pdfs, netlists etc. and a MIPS IP package
counter
- 用vhdl语言，在QuartusII下，时序逻辑电路设计（带置位的异步可逆（加1或减1）6进制计数器）-With vhdl language, in QuartusII under sequential logic circuit design (set asynchronous reversible (plus or minus) hexa counter)
lab_6
- FPGA，利用VHDL建立简单处理器（a simple processor）-FPGA, using VHDL to create a simple processor (a simple processor)
lab555
- 利用FPGA，VHDL建立工程项目，实现dicegame功能-FPGA, VHDL Establishment of Project to achieve dicegame function
lab0-part1
- 利用FPGA，VHDL建立工程项目，入门项目，实现点亮LED-Use of the FPGA, VHDL projects, entry project, lit LED
lab0-part4
- FPGA，ＶＨＤＬ，入门程序，可以在ＬＥＤ上面显示ｈｅｌｌｏ-FPGA, VHDL, and entry procedures, the LED above the display hello
lab2-part1
- FGPA,VHDL 实现１６位加法计数器，从０计数到２^１６-FGPA, VHDL 16 Addition counter counts from 0 to 2 ^ 16
fpga_12864
- 这是基于Nios II的12864液晶点亮程序，包含汉字、字符等-This is a program which is based on Nios II ,its function is light the 12864 LCD that including Chinese characters, characters
test_access_rot_edit2
- This file is VHDL code. sram access code. device name is Atera cyclone2. in quartus8.1 webedition.
Altera_VHDL
- this is vhdl code. and, or, buffer gate code device is altera cyclone2.
Fre_Div
- this is vhdl code. using Frequeny division. out device is LED. device is atera cyclone2.
rs232
- this is vhdl code. purpose of rs-232 connected with altera cyclone2.