资源列表
DE2_TV
- DE2开发板,VGA显示乐谱,键盘可操作写乐谱.-display a music score via VGA and you can write the notes on the screen one by one with a PS2 keyboard on DE2.
ss868_FallingSandGame
- DE2上,掉落个各种介质的一款游戏,玩家通过操纵键盘来画上挡板,屏幕会落下各种介质的材料,它们会显示出真实的物理特性.-On the DE2, falling a game of various media, players by manipulating the keyboard to draw on the bezel, the screen will fall a variety of media materials, they will show the true physical pr
DigiClock_v1.0
- 多功能数字钟：包含默认模式、设置模式、闹钟模式和跑表模式。已在ISE10.1工具烧录成功，烧录开发板Xilinx Spartan 3 xc3s400 pq205 speed -4 开发板烧录成功-Multi-function digital clock: contains the default mode, setting mode, alarm mode and stopwatch mode. The source code has been successfully burned in IS
sin_generate
- verilog 实现 dds正弦 函数信号发生器 verilog 实现 dds正弦 函数信号发生器-verilog achieve dds sine function signal generator verilog verilog dds sine function signal generator the dds sine function signal generator
ask-psk-qpsk
- ask，psk ,qpsk 调试解调verilog源码，是无线通信fpga设计这本书上的，比较简单的实现方式-ask, psk, qpsk debugging demodulator verilog source, is a wireless communications fpga design of this book, a relatively simple way to achieve
convertor
- vhdl语言编写的，在QuartusII下，组合逻辑电路设计（4位二进制码到BCD码的转换器）的设计，经验证无错误-Four BCD binary switch
arp
- arp协议收发的verilog代码，可以实现ARP包的收发-arp protocol verilog
lcd1602
- 本代码在FPGA上使用Verilog编程语言实现LCD1602驱动（使用状态机）-This code using Verilog programming language achieved LCD1602 driver (using the state machine) on the FPGA
seg7x6
- 本代码使用Verilog语言编写的带状态机的数码管驱动并在FPGA上得到验证！-This code uses the Verilog language with digital tube-driven state machine to be verified on the FPGA!
key_scan
- 本代码使用Verilog语言实现了矩阵键盘的驱动（含状态机）-This code uses the Verilog language matrix keyboard driver (including the state machine)
multi_adder
- 这是一个八位的乘法累加器的VHDL源代码-8 bit multiple accumulator
ADC_TLC549_CTL
- 8位串口AD549完整控制代码,红芯电子飞哥编写,完成测试-8 serial AD549 complete control of code, written in red core electrons Allen to complete the test