资源列表
TP-4748EDA-VHDL
- EDA实用技术教程VHDL版本PPT(很经典实用的资料)-EDA practical technical tutorial VHDL version of the PPT (very classic and practical information)
pipelined_fft_64
- 64点快速傅里叶变换算法的ＦＰＧＡ实现，编译仿真通过-FPGA implementation of 64-point fast Fourier transform algorithm, compiled simulation by
fifo
- 采用verilog语言的fifo设计。用notpad编辑-Verilog language fifo design. Edited using notpad
1wei_cpld240t105
- cpld240t105 vhdl写的简单的一位数码管显示程序-cpld240t105 vhdl to write a simple one digital tube display program
3_81_cpld240t105
- vhdl 编写的3—8译码器 采用的是cpld240t105-3-8 decoder using vhdl to write is cpld240t105
ADC08041wei_cpld240t105
- vhdl 编写的adc0804的程序，用在cpld240t105上面-vhdl prepared adc0804 of the program, used in cpld240t105 above
DS18B20vhdl-cpl240t105
- vhdl 编写的ds18b20的程序，用在cpld240t105上面-vhdl prepared ds18b20 of the program used in cpld240t105 above
Principles-of-computer-
- 用verilog语言描述 计算机的30条指令的实现 然后再ModelSim SE 6.1f下仿真-Verilog language descr iption of the computer 30 instruction under the simulation and then ModelSim SE 6.1f
jk_ff
- a j_k flipflop in vhdl
decoder_v
- decoder logic in decoder
mux_v
- a 4 bit mux vhdl code
alu_new
- an 8 bit 8 FUNCTION ALU VHDL