资源列表
DOT
- this vhdl code. using quartus 8.1 web edition. for using dot matrix. device name is altera cyclone2-this is vhdl code. using quartus 8.1 web edition. for using dot matrix. device name is altera cyclone2
adder
- 用vhdl语言，在 QuartusII下，用图形输入方式，实现一个4位二进制全加器，经设备验证无错误，且运行良好-In QuartusII vhdl language, graphical input, a 4-bit binary full adder verified by the equipment error-free and running well
FPGA
- 培训班的讲义，和大家分享一下，希望能够起到它应该起到的作用！-Training course handouts, and to share with you, I hope to be able to play the role it should play!
FIFOUART
- fpga实现的基于FIFO的异步串行通信代码，描述语言为Verilog-fpga-based FIFO asynchronous serial communication code descr iption language Verilog
dianzhenhanzi
- 用vhdl语言，在 QuartusII下，点阵生成小程序，用于在16*16点阵下显示名字等，经设备验证无错误，且运行良好-Vhdl language, in QuartusII lattice generate a small program used in the under 16* 16 dot matrix display name, device validation error-free, and well-run
S1_38YIMA
- 掌握 verilog 语言的设计输入，编译，仿真和调试过程；实验主要实现一个 3/8 译码器。-Master verilog language design entry, compilation, simulation and debugging process experiment to achieve a 3/8 decoder.
S2_counter
- 本实验主要是利用开发板上面的数码管实现一个十进制计数器的功能，计数范围 0000-9999，可实现循环计数。-In this study, digital development board above the pipe to achieve a decimal counter, counting range 0000-9999 cycle count.
s4_music
- 与利用微处理器（CPU 或者MCU）来实现音乐演奏相比较，用纯硬件完成音乐演 奏电路的逻辑要相对复杂很多，如果不借助于强大的EDA 工具和硬件描述语言，纯粹 使用传统的数字逻辑技术，即使是最简单的演奏电路也很难实现-Music and the microprocessor (CPU or MCU) compared with pure hardware logic of the music circuit is relatively complex, without the help o
s5_led
- 本实验是利用底板上的 LED 灯，实现LED 灯的循环点亮。-This experiment is the use of LED lights on the bottom plate, the cycle of the LED lamp is lit.
decoder4_16
- 自己照着3_8译码器写的vhdl 4_16译码器自己用max防震一下就行，没有错误-vhdl decoder4_16
adder_n
- 带进位加法器，这是照着书做的，解压以后就能在软件上仿真，没有错-This is "adder_n".
number
- 用vhdl语言，在 QuartusII下，在七段数码管上显示学号的程序，经设备验证无错误，且运行良好-Vhdl language segment digital tube display to learn the number of procedures, equipment validation error-free, and a good run in QuartusII