资源列表
FILO
- 该程序为基于Verilog实现的First In Last Out.-The program is based on Verilog implementation of First In Last Out.
picoblaze_uart_Source_code
- 用Ｐｉｃｏｂｌａｚｅ做的串口操作与控制程序，用VHDL语言编写，调试通过。-Serial do with Picoblaze operation and control procedures, using VHDL language, through debugging.
Berlekampalgorithm_Verilog_hdl
- RS编码器是Reed Solomon编码器的简称，它是目前最有效、应用最广泛的差错控制编码方法之一。-The RS encoder Reed Solomon encoder referred, it is the most effective, the most widely used error control coding method one.
VHDL
- VHDL XIAZAI GOOG VERYGONNGD
tbxsp010
- 用VHDL语言编写的代码，以供大家学习和交流，方便大家学习！-prepared using VHDL code for all to study and exchange to facilitate learning!
digital_filter
- 数字滤波器VHDL源码，在matlab下仿真-Digital filter VHDL source code, under the simulation in matlab
generic_fifos
- 用HDL语言编写的通用fifo源码，通过对fifo的宽度和深度进行配置，可以产生我们所需要的fifo，还包括fifo的测试程序和仿真Makefile脚本-with HDL prepared by the General fifo source, fifo of the breadth and depth configuration, can produce what we need fifo. also included fifo testing procedures and simulatio
adder_latch
- 用verilog编写了一段地址锁存器的代码，希望能帮助大家！-Prepared using a verilog code address latch, hoping to help you!
Arbitrary-points-frequency
- 任意分频用verilog实现，偶数分频，奇数分频-Arbitrary points frequency
memoryverilog
- 一个关于MEMORY设计的原代码,使用VERILOG编写的 希望对大家有些帮助-one of the original Memory design code prepared by the use of verilog we hope to help some
LIP1732CORE_system_mbus_arbiter
- System Verilog M bus arbiter module
half_clk
- 将clk信号进行二分频，输出频率为其一半的信号-divide