资源列表
taxi
- 基于顶层模块用Verilog HDL设计的出租车计费系统，4位精度-Based on the top module use Verilog HDL design taxi billing system, four accuracy
2402-dld
- Multisim® is a schematic capture, simulation, and programmable logic tool used by college and university students in their course of study of electronics and electrical engineering. Multisim is widely regarded as an excellent tool for classroom a
xinhao
- 简易信号发生器，可输出三种波形，递增锯齿波发生器模块，正弦波发生器模块，方波发生器模块，波形选择器模块，vhdl-Simple signal generator can output three waveforms, incremental sawtooth generator module, the sine wave generator module, a square wave generator module, waveform selector module, vhdl
VGA
- 通过对其编程可输出RGB三基色信号和HS 、VS行场扫描同步信号。当 CPLD接受单片机输出的控制信号后，内部的数据选择器模块根据控制信号选通相应的图像生成模块，输出图像信号，与行场扫描时序信号一起通过15针D型接口电路送入VGA显示器，在VGA显示器上便可以看到对应的彩色图像。-Through its programming output RGB trichromatic signals and synchronization signals HS, VS line field scannin
Part-
- data transfer from one multiport ram top other multi port ram. it is a system generator compatible bile
pci-express-system-architecture.pdf.tar
- PCI Express is a high performance, general purpose Serial I/O Interconnect defined for a wide variety of future computing and communication platforms. The basic premise of PCI Express is that the host PCI software remains compatible with an e
sv_mux.tar
- it is the verification code written in system verilog for the verification of 4:1 mux and with functional coverage
mux_ovm_full-cover.tar
- this 4:1 mux verification code which is written in ovm and with functional coverage-this is 4:1 mux verification code which is written in ovm and with functional coverage
pci_express.pdf.tar
- in this pdf the internal architecture of pci has explained. e.g. transaction layer data link layer ,physical layer-in this pdf the internal architecture of pci has explained. e.g. transaction layer data link layer ,physical layer
make-file-vcs.tar
- this the verilog code of 4:1 mux and i have used case statement to explain the logic of this mux-this is the verilog code of 4:1 mux and i have used case statement to explain the logic of this mux
LineBuffer---shifttaps
- 基于移位寄存器的线缓冲，从alt中提取出来，方便使用-Line Buffer。rar
PID-FPGA-source-code
- 用VHDL写的PID控制器，可以在FPGA上实现-PID controller can be written using VHDL on FPGA