资源列表
Audio_test
- 公司开发板程序E-PLAY-EP4CE40 Audio源码-Company development board program E-PLAY-EP4CE40 Audio Source
TV_VGA
- 公司开发板程序E-PLAY-EP4CE40 VGA图像处理源码 -A Company development board program E-PLAY-EP4CE40 VGA image processing source code
verilog-example
- verilog基础实验，包括篮球计数器，序列检测计等-verilog based experiments, including basketball counter sequence detector
radar-controller-design-
- 某个雷达控制器的实现，当中的一些思想还是值得借鉴的，这是哈工大的硕士毕业论文，参考价值很大！-The realization of a radar controller, among some of the ideas or worth learning, This is HIT master' s thesis, a great reference value!
EDA4--3
- 实现的电子钟，资料非常全面，是一次课程设计的大作业，完成的质量很高。-Achieve the electronic clock information is very comprehensive, curriculum design job, completed high quality.
lab2_Freq_20120510
- 用verilog写的频率计，上课的时候用的。Spartan - 3E开发板。-verilog
elevator
- verilog写的控制电梯的代码。输入多少则计数到那个点后停止计数-elevator controler
UART_Transmitter_Arch
- 自己编写的带有FIFO的UART串口发送模块，代码通过状态机实现，开发语言是Verilog-I have written to the FIFO UART serial transmit module code through the state machine implementation, development languages Verilog
verilog-example
- 以前用XC3S400AN的fpga开发板做的实验，供新手参考-XC3S400AN fpga development board to do the experiment, for the novice reference
fenpin
- 实现了1到62553的任意分频，且文件中包含测试文件，是个不错的选择。-1-62553 any divide the file containing the test file, is a good choice.
EDA
- EDA培训.分频电路设计.有限状态机.Modelsim仿真.FPGA片内资源利用-EDA training. Divider circuit design. Finite state machine. Modelsim simulation FPGA chip resource utilization
no1
- VHDL做的16位并行输入转16同步串行输出-VHDL to do 16-bit parallel input to 16 synchronous serial output