资源列表
digital_correlator
- 16位高速数字相关器流水线 -16 high-speed digital correlator lines 16 lines high-speed digital correlator
myproj
- 使用vhdl语言设计波形发生器，产生正弦波，方波，三角波，锯齿波，实现频率，幅度可调。项目包附有设计说明和资料。-Waveform generator using vhdl language design, produce sine, square, triangle, ramp, realize the frequency, amplitude adjustable. Project package with design specifications and data.
DMAC
- 该程序实现在ALTERA FPGA 上搭建NIOS系统，实现DMA 传输-The program built on the ALTERA FPGA NIOS system, DMA transfer
epcs35f
- 该程序实现了在ALTERA FPGA上搭建NIOS系统，实现程序在EPCS4上保存，在内部RAM 上运行-The program to build on in the ALTERA FPGA NIOS system, program EPCS4 saved on the internal RAM to run
F35RUNFILE
- 该程序在ALTERA FPGA 上搭建NIOS系统，把程序保存在外置的NOR FLASH中并实现开机运行-The program is built on ALTERA FPGA NIOS system, the program stored in the external NOR FLASH and implemented in switched
UART_VERILOG
- 该程序实现在ALTERA FPGA 上使用VERILOG HDL语言实现串口通信。-The program in ALTERA FPGA VERILOG HDL language used on serial communication.
载波发生器VDHL语言实现！
- 实现正弦载波的产生。用于PSK，qpsk等各种调制。
sram_test
- is61lv25616简单的verilog程序，完成sram读写-is61lv25616 simple verilog program, complete sram read and write
tlc549
- 使用tlc549实现ad变换并在led上显示出来-Use tlc549 achieve ad transform and led on display
YIWEIJICUNQI
- 两种移位寄存器的设计，分别为通用移位寄存器跟桶形移位寄存器-Two kinds of shift register design, namely, universal shift register with the barrel shifter
CHUANKOU
- 通过对时钟分频，串口接收和发送以及串口调试程序的编写实现数据的接受和发送-Through the clock divider, and a serial port receive and transmit serial debugging procedures for the preparation of the receiving and sending data
shixuzhuangtaiji
- 通过verilog hdl语言实现对时序状态机的编写-By verilog hdl language for writing timing state machine