资源列表
arbiter_ip
- Arbiter code for simulation purpose
counter
- Counter Code to test the functionality on Altera devices.
Generic_Pattern_Detector_3bit
- Generic Pattern detector circuit
shuzibiao
- xilinx下使用vhdl编写数字表 具有启动、复位、暂停、暂停后继续计时等功能 能显示的秒计数时间精确到小数点后第二位，即能显示**.**s -xilinx vhdl prepared using digital watch with a start, reset, pause, pause, continue after the timer function can display the seconds counting time accurate to the second
writereadflash
- 这个是用VHDL实现FPGA对FLASH的读写。-This is achieved using VHDL FLASH FPGA to read and write.
Manchester-code-of-VHDL-program
- 利用FPGA实现硬件的VHLD语言的Manchester code。-Hardware implementation using FPGA VHLD language Manchester code.
dingceng
- 简单的地铁售票系统，可以实现1元，2元，5元投币，自选票数-Simple subway ticketing system that can achieve 1 yuan, 2 yuan, 5 yuan coin, optional Votes
Altera_Quartus_SPI
- SPI on Quartus Altera witn testbensh simulation
FPGA_SPI_master
- master spi code for quartus
SPI_on-quartus
- spi master code for fpga quartus altera
SPI
- spi master code for fpga quartus altera
SPI-verilog
- spi master code for fpga quartus altera