资源列表
EX5
- 基于FPGA的VGA显示，可以根据不同的需要更改显示的图形。-FPGA-based VGA display, you can change the display according to the different needs of the graphics.
VHDLfiles
- this rar file includes some simple VHDL codes for students.
alarm
- VHDL，多功能数字钟：具有年、月、日、时、分、秒计数显示功能，以24小时循环计数；具有整点报时功能；可以对年、月、日、时、分及秒进行单独校对，使其校正到标准时间-VHDL, multifunction digital clock: a year, month, day, hour, minute, seconds count display features a 24-hour cycle The whole point timekeeping function possible for
DB25-JATA10
- 这是用于ALTERA公司CPLD/FPGA芯片的并口下载器，里面的电阻、电容的参数都是对的，是成熟产品的并口下载器设计方案。-This is used ALTERA chip CPLD/FPGA parallel port download, parameters of resistance, capacitance inside is all right, is a mature product parallel download device design scheme
EP1C3T144_develop
- EP1C3T144最小系统板原理图，包括完整的电源电路、下载配置电路、基本测试电路。-EP1C3T144 minimum system board schematic diagram, including the power supply circuit, complete download configuration circuit, basic circuit.
VGA
- VGA彩条显示VHDL程序，横竖彩条、棋盘格式-VGA color display VHDL program, anyway color bars, checkerboard format
FIR
- 低通、十阶FIR滤波器，Quartus II开发环境。-Low pass, ten-order FIR filter, Quartus II development environment.
PLL
- VHDL硬件描述语言实现PLL锁相环功能-VHDL hardware descr iption language PLL to function
TAXI
- VHDL硬件描述语言实现出租车计费器的功能，不同时段，不同行驶状态费用可以调节-VHDL hardware descr iption language taxi meter' s functions, different times, different running state fee can be adjusted
F_counter
- VHDL硬件描述语言实现自适应频率计的功能，数码管显示，输入主频50M-VHDL hardware descr iption language to achieve adaptive frequency meter function, digital display, input frequency 50M
spi_inf_middle_filter
- 采用spi接口读取adc数据，存储数据，将数据进行中值滤波处理，最后通过总线接口发送到dsp处理器-spi interface adc sample program with middle filter process.
UART
- 串口通讯，光纤通讯，需要中间一个CPLD的转换，这个转换需要一种自适应的算法。-Serial port and serial port and optical fiber communication and optical fiber communication serial communication serial port and serial port and optical fiber communication and optical fiber communication seria