资源列表
seryal2paraller
- SERYAL TO PARALEL CINVERT VHDL ISE
qdq
- 用VHDL语言实现四路抢答器功能，抢答之后不能再抢答，除非主持人按下复位键。可以显示四个选手分数，显示答题倒计时的时间，主持人可以控制加减分，分数通过显示屏显示。使用软件Quartus Ⅱ，可以将程序导入FPGA并能运行。有竞争模块，显示模块，分频模块，加减控制模块，计数器模块，蜂鸣器模块，译码模块，计分器模块，锁定模块等。-VHDL language with four Responder function can not answer after answer, unless the hos
viterbi
- 维特比译码相关verilog代码，基于802.11g协议的。。
TSW1250EVM_FPGA_BIT_FILE
- TSW1250开发板源代码文件，FPGA开发设计LVDS信号解串器-TSW1250 development board source code files, FPGA development and design deserializer LVDS signals
ps_music_ram
- 用ps/2键盘实现电子琴，利用ram可读出预存的曲子，也可以可写如弹凑的曲子-With ps/2 keyboard to achieve organ, using the ram read out the stored song, it can be written as the song playing Minato
FirFullSerial
- 15阶低通，具有线性相位的全串行FIR滤波器结构的fpga实现-15-order low-pass, with a linear phase FIR filter structure full serial fpga implementation
I2C_slavemodule_simulation
- i2c slave module simulation codes
fpga_uart
- verilog编写的简单串口收发代码，quartues II 下cyclone II 测试通过-prepared by the simple serial transceiver verilog code, quartues II test under the cyclone II
adcontrol
- 采用VHDL编写的FPGA的AD转换读取逻辑。AD器件为TI ADS7961 -FPGA using VHDL prepared to read the AD conversion logic. AD device is a TI ADS7961
dacontrol
- 采用VHDL编写的FPGA的DA转换读取逻辑。DA器件为TI TLC5628 -Prepared using VHDL FPGA-DA converter reads logic. DA devices are TI TLC5628
(15-7-2)BCH
- Verilog HDL 语言编写的（15，7,2）BCH编码和译码功能-Verilog HDL language (15,7,2) BCH encoding and decoding functions
DE2_70
- DE2-70开发板实验例程 中文非官网资料-DE2-70 development board test routines Chinese non-official website information