资源列表
EDA_2
- 简易计算器，可四位同时显示，加减法有指示-Simple calculator four also showed that addition and subtraction with instructions
EDA_2_2
- 键盘扫描，可识别按键，单位显示，但无防抖-Keyboard scanning, can identify keys, display unit, without stabilization
half_adder
- 半加器，数字系统中，二进制运算可转换为加法运算，所以加法器是一种重要的逻辑部件。已成功运行过。-Half adder, digital systems, the the binary operation can be converted to addition operation, the adder is an important logical parts. Has been run successfully.
dac
- 运用ISE13.2完成的DAC工程。完成一个数模转换的作用。-Use ISE13.2 completed DAC works. To complete a digital-analog conversion effect.
16bits_multiplier
- 这是一个有符号的16位乘法器的设计，包含详细的设计报告和全部的verilog代码。乘法器采用booth编码，4-2压缩，超前进位结构-This is a signed 16-bit multiplier design, detailed design reports and contains all of the verilog code. Multiplier using booth encoding ,4-2 compression, lookahead structure
SRAM6bit
- sram 6bit仿真模型，verilog编写-sram 6bit simulation model, verilog prepared
RTL
- verilog编写的关于使用MENTOR的MBISTArchitect进行momery的自测试代码，包含测试算法模型，SRAM,ROM模型-verilog prepared by the use of MBISTArchitect for momery MENTOR self-test code, including test algorithm model, SRAM, ROM model
PCI
- PCI总线仲裁参考设计Verilog代码，包括一些说明文件-PCI bus arbitration reference design Verilog code, including some documentation
spi
- 该程序是一个可完成订制化的SPI双向总线接口，时钟相位、极性，以及分频比全部可通过寄存器进行配置，已经在ISE下通过综合，占用资源少，强烈推荐 -The program is a complete custom of SPI bidirectional bus interface, clock phase, polarity, and the divider ratio can all be configured through the register, has been in the I
fpga-jpeg
- 包含DCT变换，RGB2YCBCR,JPEG等多个verilog代码及工程-Contains DCT transform, RGB2YCBCR, JPEG and many other verilog code and project
RT_Ethernet
- 实时以太网MAC层协议控制器。注：100M全双工-Real-time Ethernet MAC layer protocol controller. Note: 100M full duplex
serial
- 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。 程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。 串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值 是0x104，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通 信同步-The mod