资源列表
ov7602
- FPGA的vga显示，ise环境下，验证过好用-FPGA-vga display
VHDL_Code
- 描写nco的完整程序，采用很简介的算法，对大家应该很有用-The complete program descr iption nco, using a very brief introduction of the algorithm, we should be very useful
WBL
- 智能微波炉实现，时分秒计时倒计时，蜂鸣器，显示火力等，VHDL实现-Intelligent microwave oven, when minutes timer countdown, buzzer, according to fire, etc
JK-flip-flop
- 带有异步置位复位端的上升沿触发的JK触发器，使用VHDL语言实现的-Asynchronous reset terminal set with rising edge triggered JK flip-flop, the use of VHDL language
spi_interface_premier_slave
- verilog版的spi接口的slaver部分程序-verilog version of the spi interface slaver part of the program
traffic
- 一个简单的交通灯控制器，交通灯显示用实验箱的交通灯模块来显示。系统时钟选择时钟模块的1Hz时钟，黄灯闪烁时钟为1Hz，红灯15s，黄灯5s，绿灯15s。-A simple traffic light controller, traffic lights display module test box to display the traffic lights. System clock selection 1Hz clock module clock, flashing yellow clock
chaoqianjinweiliuweijiafaqi
- 六位加法器（逻辑门电路实现）verilog 语言编写-6 bit Adder
ll_clock
- 数字电子钟的设计，振荡器产生稳定的高频脉冲信号,作为数字钟的时间基准,然后经过分频器输出标准秒脉冲。秒计数器满60后向分计数器进位,分计数器满60后向小时计数器进位,小时计数器按照“24翻1”规律计数。计数器的输出分别经译码器送显示器显示。计时出现误差时,可以用校时电路校时、校分。- Digital electronic clock design, stable high frequency oscillator generates a pulse signal as a digital c
ALU
- verilog编写，八位ALU，加减与或比较-verilog prepared eight ALU, subtract, or compare with
divider_testbench_vhdl_611508553
- 分频器的testbench测试，可联合仿真使用-Divider testbench test
alu_testbench_vhdl_689102300
- ALU的testbench测试，可联合仿真使用-The ALU testbench test can be co-simulation using
SONGER
- 利用ABEL语言设计一个多模计数器，对实验台上的100KHz进行分频，产生8种希望的频率。将8种频率的信号输入喇叭，产生8种不同声音，驱动喇叭的方波占空比应是50％，以增大音量。频率调制成功后，将8种音调按一定的优先级输出。-ABEL language use to design a multi-mode counter, the experimental stage 100KHz dividing to produce eight kinds of the desired frequency.