资源列表
PIC16F5X-RISC
- PIC16F5X-大型RISC处理器-代码实现集合,其中包含工程，说明文档-PIC16F5X-Large RISC processor- code set, which includes engineering, documentation
Verilog-HDL--MODEL
- Verilog HDL程序设计教程verolog代码设计，包含各种基本代码-Verilog HDL programming tutorial verolog code design, includes a variety of basic code
8051-Verilog
- 8051的Verilog源代码，包含说明文件，RTL文件，工程等-8051 Verilog source code, including documentation, RTL files, engineering, etc.
digital-timer
- 数字时钟的verilog代码，以仿真编译通过，可直接用-Digital clock verilog code which is compiled and simulated and can be directly used
SDRAM
- 芯片测试资料，主要包括lcd，时钟，计数器分频器的设计-Chip test data, including lcd, clock, counter divider design
aaa
- 这是一个基于fpga的，用VHDL语言编写的，关于50M的分频器。-This is an fpga-based, using VHDL language, about 50M divider.
qiangdaqi_stable_version
- 多功能抢答器，包括时钟分频模块，数码管显示模块，ps2键盘模块，流水灯模块等-Multifunction Responder, including clock divider module, the digital display module, ps2 keyboard module, water lights module
BCD_divid_new
- VHDL语言编写的8位BCD除法器，可以实现浮点数计算，只支持正数运算，并用isim进行仿真-VHDL language 8 BCD division, can achieve floating-point calculations, which only supports a positive number arithmetic, and use isim simulation
verilog-hdl
- 很少有完整介绍ISE环境下FPGA开发的资料，这是在Xilinx ISE开发平台下进行FPGA设计比较好的教程，感觉挺不错的-there is few full descr iption ISE FPGA development environment information, which is in the Xilinx ISE development platform for FPGA design is a good tutorial, I feel pretty good
100240217
- 心率监测仪 1，正常人心率为60到100，每6秒为一个单位，检测心跳是否正常，显示其心率值 2.心跳如果不够长，发生报警，心率过缓或心率过快的报警声音不同 3.心脏停止跳动，用连续的报警声 4.心率正常时闪烁显示心率，并伴有报警声音 5.心率正常解除报警 6.没按下查询键一次，三秒显示错误心率，三秒显示错误心率时间-Heart rate monitor 1, normal heart rate of 60 to 100, every six seconds as a un
BCD_subtracter
- VHDL编写的7位BCD减法器，可实现带小数点减法运算。-VHDL, 7 BCD subtraction, which can be achieved with a decimal point subtraction.
display_input
- 用VHDL控制LCD12864输出指定文字-Using VHDL output control LCD12864 specified text