资源列表
UART
- 實作UART 介面 4 byte 傳送 或 4 byte 接收 開發環鏡 quartus 且 附模擬檔-4 byte real interfaces for UART transmission or 4 byte receive loop mirror quartus and the development of simulation files attached
MIT_Press-Circuit_Design_with_VHDL(2005)
- MIT Press - Circuit Design with VHDL (2005)
DDS_verilog
- 通讯中常用的dds模块的verilog源码打包下载-Communications commonly used in dds module verilog source code package to download
fre_devider_double
- 硬件中常用的偶分频电路的Vhdl源码，很有用-Even commonly used in hardware divider circuit Vhdl source code, useful
FPGA_VGA_TEXT-Quintin_Immelman
- FPGA VGA TEXT - Quintin Immelman -implementation of text on fpga in VHDL-FPGA VGA TEXT - Quintin Immelman -implementation of text on fpga in VHDL
VHDLscounter
- 通过VHDL自行设计的一个秒表共有4个输出显示，分别为、十分之一秒、秒、十秒、分，所以共有4个计数器与之相对应（3个十进制计数器，一个6进制计数器用来对十秒进行计数），整个秒表还需有一个复位信号和一个精确的10HZ时钟信号。-Of a self-designed by VHDL stopwatch showed a total of four outputs, namely, one-tenth of seconds, seconds, ten seconds, minutes, so a to
DDSTHEORY
- 详细介绍了DDS原理，文档容易理解，是硬件开发者不错的选择-Details of the DDS principle, the document easy to understand, is a good choice for hardware developers ....
logicSythesisBuildGate.pdf
- 逻辑综合的一些使用tips，做芯片前端的要-Some of the use of logic synthesis, tips, do-chip front-end to have a good look
FPGA
- FPGA的作品，比较正规的veilog代码-FPGA-works, a more formal veilog code
HDB3
- HDB3编码器与译码 HDB3编码器与译码-HDB3 encoder and decoder
FSK
- FSK调制与解调VHDL程序及仿真FSK modulation and demodulation process, and VHDL simulation-FSK modulation and demodulation process, and VHDL simulation