资源列表
uart_rx
- Universal Asyncronos Received Transmitter
mod_m_counter
- Frequence Divisor for the Universal Received Transmitter
fifo
- First Input Fisrt Output Register
uart_tx
- Interface for Transmitter UART
uart_test
- Test For The Universal Asynchronos Received and Transmitter
liangzu
- 一小段梁祝音乐播放范例的文件，希望对学习verilog的初学者有所帮助。-Butterfly short sample music files, want to learn verilog beginner help.
CODE
- TCD1206图像传感器 VHDL 驱动说明及编程设计-TCD1206 VHDL
songer
- 根据给出的乘法器逻辑原理图及其各模块的VHDL描述，学习利用数控分频器设计硬件乐曲演奏电路-According to the logic given multiplier module schematic and its VHDL descr iption, learning to use the numerical design of the hardware musical performances divider circuit
SRAM_Proj
- SRAM 读写VERILOG HDL源码-SRAM read and write VERILOG HDL source code
cf_fft
- FFT using C and VHDL. can compute upto 1K, 2K and 4K in radix 2.
EMCRTL
- RTL Code for Design of Extarnal Memory Controller for Accessing Asynchronous SRAM of size 512Kx16
fftandifft
- this is a code in VHDL for FFt and its inverse. also the programs are given in matlab