资源列表
DiceFinal
- vhdl source code for dice game
ad0809
- adc0809 转换，verilog代码-adc0809 conversion, verilog code
VHDL_implementation_1KHz_sine_wave_generator
- 用VHDL实现1KHz正弦波发生器，编译器是Quartus II 5.4-1KHz sine wave generator using VHDL implementation, the compiler is a Quartus II 5.4
verilog
- 我用过的verilog大量历程，适合初学者，-verilog lot of history, suitable for beginners
CLAAdd
- This zip folder contains the Carry look ahead in verilog HDL
VHDL_Data
- 潘松的VHDL使用教程，已经制作书签，阅读方便，是学习VHDL新手的必备资料，FPGA/CPLD开发者可以参考的资料，-Pinson use of VHDL tutorial have produced bookmarks, reading easy to learn the essential information on VHDL novice, FPGA/CPLD developers can refer to the information,
coe3dq4_lab1_2009
- Verilog HDL键盘消抖程序，Verilog HDL键盘消抖程序-debouncing code in Verilog HDL
VHDLmath
- 这是一篇关于VHDL各种算术算法的文章，希望对各位有帮助 -This is a variety of mathematical algorithms on the VHDL articles, want to be helpful
cw
- control word generation
dmfilter
- gps接收机伪码捕获时采用的匹配滤波器，能完成接收码的捕获。-gps receiver pseudo-code used to capture the matched filter, receiving yards to complete the capture.
dual_RAM
- vhdl语言编写的双口ram及testbench,模块可以在modelsim里进行时序和功能仿真。-vhdl language of the dual-port ram, and testbench, modules, conducted in the modelsim timing and functional simulation.