资源列表
vga-timing-generator
- VGA时序产生，可用于VGA接口的时序控制-VGA Timing Generator
COMPLETE-UART_16
- the project is complete a UART implementation where 16 UART are connect with top module for aerial applications-the project is complete a UART implementation where 16 UART are connect with top module for aerial applications
FPGA_1602
- 在1602上实现汉字显示！而且是两个1602拼接共同显示一个汉字！自己做的，运行成功！-In 1602 realized characters on display! And is stitching together two 1602 displays a character! Do it yourself, run successfully!
fft
- 1024点，8位定点数的FFT计算，代码精炼，注释全面值得下载-1024 points, FFT calculation eight fixed-point code refining, comprehensive notes worth downloading
cpu
- 用vhdl实现了具有流水的cpu，实现30条基于mips指令的指令集-Achieved with vhdl cpu with water, to achieve 30 mips instruction based instruction set
DE2_video_pass_demo-rww
- 视频发射源发射信号，基于DE2115fpga平台的视频信号显示与处理-Transmitting the video signal transmission source, based on a video signal display DE2115fpga platform and processing
1112
- 基于fpga平台的与HMI屏幕的串口连接实现简单图像的显示和触屏操作-Fpga based platform serial connection with HMI screen image display and simple touch-screen operation
digital-tube
- 基于FPGA平台，实现3*3按键在单位数码管上显示相应字符，再次输入其他数字后，将以前数字在四位数码管实现数字移动-FPGA-based platform, 3* 3 button to display the corresponding character in the digital unit, enter the other numbers again, the figures in the previous four digital tube digital mobile
test- clk and reset generation
- test- clk and reset generation
Ring0
- température FPGA projet fichier te mpérature FPGA projet fichier te mpérature FPGA projet fichier-température FPGA projet fichier température FPGA projet fichier température FPGA projet fichier température FPGA projet fichier température FPGA projet
ChengFaQi_mux16
- 实现16位乘法器 并有modelsim仿真文件-The realization of the 16 bit multiplier and Modelsim simulation file!!!!!!!!!!!!!!!!!!!!!!!!
divcnt
- 基于Lattice XO2系列的简易分频器-Based on Lattice XO2 series of simple divider