资源列表
SW-LED
- this code show to use Altium to coding Switch and LED on FPGA-CPLD -this code show how to use Altium to coding Switch and LED on FPGA-CPLD
SW-BIZ-REL
- this code show to use Altium to coding Relay and Switch and Beezer on FPGA-CPLD -this code show how to use Altium to coding Relay and Switch and Beezer on FPGA-CPLD
SEG-1
- this code show to use Altium to coding Single 7 Segment on FPGA-CPLD -this code show how to use Altium to coding Single 7 Segment on FPGA-CPLD
taximeter
- 利用 VHDL语言、PLD设计出租车计费系统,采用VHDL编写租车计费器系统程序,采用MAX+PLUSII软件作为开发平台,进行了程序仿真,验证设计实现了出租车 计价器的相关功能。 .-Using VHDL, PLD design taxi billing system, using VHDL prepared Car billing system procedures, using MAX+PLUSII software as a development platform for the si
FPGA00Verilog
- 该文件能够用verilog语言实现FPGA与电脑的串口通信，高效准确。-This file can use verilog language implementation of FPGA and computer serial port communication.
fsm
- verilog四状态状态机 带异步清零端和测试向量 mealy型状态机 很好用哦 -verilog four state machine with asynchronous clear end and test vectors mealy-type state machine oh well
asyn-fifo
- 功能就是一个FIFO，first in first out！避免跨时钟域的亚稳态-Function is a FIFO, first in first out! To avoid the cross clock domain metastable
DES_des
- DES 使用一个 56 位的密钥以及附加的 8 位奇偶校验位（每组的第8位作为奇偶校验位），产生最大 64 位的分组大小。这是一个迭代的分组密码，使用称为 Feistel 的技术。-DES uses a 56 bit key and an additional 8 bit parity bit (n = eighth as the parity bit), the largest 64 bit packet size. This is a block cipher an iterative, u
tlc549adc
- FPGA AD数据采集模块，实现模拟信号到数字信号转换。-FPGA AD data acquisition module, the analog signal to digital signal conversion.
you_ran
- 串行UART接收，采用VHDL语言，供参考-Universal Asynchronous Receiver/Transmitter
FreCounter
- 中国地质大学sopc实验课程序。大三下学期！-China University of Geosciences sopc Lab program. Junior next semester!
DPD_project
- 预失真算法中，包络解波部分的verilog代码，有部分错误-envelope calculation of DPD algorithm ，verilong HDL language