资源列表
caiyang
- 数字视频光端机发送端采样过程编码二十字有木有-Digital Video Optical sending end sampling procedure coding
ssram_latest.tar
- SSRAM接口,就是同步静态随机存取存储器接口整个工程文件，包括从前端verilog设计到后端仿真的整个工程-SSRAM interface is synchronous static random access memory interface entire project, including the design from the front to the back verilog simulation of the entire project
PGen
- double pulse generator start with trick signal control time between pulse by serial loading
seg22
- 用VHDL语言编写，在cycloneii EP2C5T144C8N上实现计数器在数码管上的显示-Using VHDL language, on cycloneii EP2C5T144C8N achieve counter displayed on the digital control
Puncture
- OFDM编码技术中，删余模块的编码，包括了2/3和3/4-OFDM coding, the coding puncturing module, including 2/3 and 3/4
counter
- 同步清零的可逆计数器，带时钟分频 Verilog HDL语言编写-Synchronous clear reversible counter with clock divider Verilog HDL language
ds18b20
- ds18b20实现的温度采集系统，分为接口时序和温度转换为bcd代码两部分。-The temperature acquisition circuit design based on FPGA
ADPLL
- This paper presents the ADPLL design using Verilog and its implementation on FPGA. ADPLL is designed using Verilog HDL. Xilinx ISE 12.1 Simulator is used for simulating Verilog Code. This paper gives details of the basic blocks of an ADPLL. In this p
LED_Counter
- this code show how to use Altium to coding LED Counter on FPGA-CPLD
LEDglow
- this code show how to use Altium to coding LED glow on FPGA-CPLD
RS232
- this code show how to use Altium to coding RS232 on FPGA-CPLD
SEG_BUS
- this code show to use Altium to coding 7 Segment BUS on FPGA-CPLD -this code show how to use Altium to coding 7 Segment BUS on FPGA-CPLD