资源列表
Building-Counters-Veriog-Example
- building counters in vhdl
New-Text-Document
- mulitiplier and analog to digital
verilog dds
- 用verilog 实现dds功能，可以实现方波，三角波等波形的输出
FPGA_LED
- NIOS II上实现，包含led的的控制verilogHDL，原理图的设计等等，直接用nios II打开就可以使用-NIOS II achieve control of verilogHDL contain led, schematic design, etc., directly nios II can be used to open
Float_add
- 该源码利用Verilog HDL语言成功实现了浮点数的加法运算，包括全部工程以及Verilog 源码，经验证，该程序成功实现了浮点数的加法。-The use of Verilog HDL source language of the successful implementation of floating-point addition operation, including all engineering and Verilog source code, proven, successful
The-four-locks-Verilog-based-design
- 基于Verilog的四位密码锁设计，采用有限状态机进行编写-The four locks Verilog-based design, finite state machine for the preparation
Verilog_UART
- the file use verilog HDL to realize uart.it contain recive and transmit.-the files use verilog HDL to realize uart.it contain reciver and transmitor.
Quartus_FPGA
- this a smal programme that convert a binary code to a gray code, and a file that expalin the DE2 pin assignements-this is a smal programme that convert a binary code to a gray code, and a file that expalin the DE2 pin assignements
Quartus_FPGA_detect
- this a simple VHDL code on quartus that can detect a sequence of binary input, this files contain an DE2 pins assignements -this is a simple VHDL code on quartus that can detect a sequence of binary input, this files contain an DE2 pins assigne
eda
- 用verilog硬件描述语言编写的电子琴工程，实现手动弹奏21个音符，自动播放内置音乐，在显示器上模拟显示按键等功能。-Using verilog hardware descr iption language organ works, play 21 notes for manual, automatic built-in music player, analog display buttons on the monitor and other functions.
dpll
- 用verilog编写的全数字锁相环，包括鉴相器，模K计数器，加减脉冲模块和分频模块，都经过验证-verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider
EDA-clockr
- EDA技术之数字时钟，带有定时闹钟功能-The EDA technology digital clock, alarm clock with timer function. . . . . . . . . . .