资源列表
vhdl
- vhdl程序集锦，适合一些学quartus的初级人员学习了解-vhdl program highlights for some of the school' s junior staff learn about quartus
FIR
- 使用Verilog语言编写的FIR滤波器,在Xilinx Spartan-6上运行通过,是很好的Verlog程序-Using Verilog language FIR filter, the Xilinx Spartan-6 run through, is a very good program Verlog
vga_640x460_spirte
- 使用Verilog语言编写的vga显示条纹的程序,可以在显示器上显示彩带,在Xilinx Spartan-6上运行通过,是很好的Verlog程序-Using Verilog language program vga display stripes, ribbons can be displayed on the monitor in the Xilinx Spartan-6 run through, is a very good program Verlog
SRAM
- 使用Verilog语言编写的SRAM读写程序,不用添加IP核,在Xilinx Spartan-6上运行通过,是很好的Verlog程序-SRAM using Verilog language literacy program, do not add the IP core in Xilinx Spartan-6 run through, is a very good program Verlog
brom_16x8
- 使用Verilog语言编写的ROM读写程序,使用IP核,在Xilinx Spartan-6上运行通过,是很好的Verlog程序-ROM using Verilog language literacy program, the use of IP core in Xilinx Spartan-6 run through, is a very good program Verlog
bram_16x8_top
- 使用Verilog语言编写的RAM程序,可以双向读写,在Xilinx Spartan-6上运行通过,是很好的Verlog程序-RAM using Verilog language program, you can bi-literacy, in the Xilinx Spartan-6 run through, is a very good program Verlog
two_dimension_fpga
- FPGA实现模糊控制,可以应用于各种控制相关工程之中-FPGA Implementation of Fuzzy Control
uart
- 基于wishbone的 uart 通信设计-The uart communication design based wishbone
static-timing-analyze
- 特权同学主讲的FPGA设计的时序约束专题（STA部分）-Speaker privileged classmates timing constraints for FPGA design topics (STA section)
altera
- 用于串口与光纤通信，在232，以及485与光线的转接，需要自适应的算法。-For serial and fiber optic communications, in 232, and 485 and the light switching, requires adaptive algorithms.
EP2C70F896C6N-pins
- 将VHDL程序下载到DE2开发板，引脚分配时需要知道的芯片每个引脚功能-VHDL program will be downloaded to the DE2 development board, you need to know when the pin assignments for each pin of the chip functions
phase_measure
- 这是一个计算两个同种类型的信号的相位差的Verilog实现的代码-This is a calculation of two signals of the same type of implementation of the code phase of the Verilog