资源列表
斐波那契数列Verilog实现
- 斐波那契数列Verilog实现
feibonaqi
- 斐波那契数列，用VErilog语言实现非常好-Fibonacci sequence, using VErilog language is very good ha ha ha ha ha ha ha
HSD_070PFW3(P0703)
- 瀚彩P0703模组,FPGA驱动代码,画面：黑、白、红、绿、蓝、棋盘格-Han Choi P0703 modules, FPGA driver code, the screen: black, white, red, green, blue, checkerboard
fpga
- 简易数字存储示波器verilog源代码 经过EP2C8Q208C8验证-Simple digital storage oscilloscope verilog source code has been verified EP2C8Q208C8
CHENG
- 这是关于psk解调与调制器的VHDL语言的程序 是关于FPGA的实现，希望能帮助各位-This is about psk demodulator and modulator VHDL language program is implemented on the FPGA, hoping to help you
Enc_With_Punc---2011-11-28-v3.0
- Viterbi 译码打孔和去打孔代码, ,VERILOG 代码，自己写的，包含时钟打孔，-Viterbi Decoder With Puncture and Depuncture， Verilog Code，clock puncture ,
ceping1
- 基于ＦＰＧＡ的一个频率计的设计，希望对有需要的朋友们有所帮助。很是简单的一个东西，希望大家一起改进-FPGA-based design a frequency counter, and I hope there is a need to help friends. It is simply a thing, I hope everyone Improved! ! !
I2C_slavemodule
- Verilog I2C 转SPI 总线代码，在MAX EP240上成功使用，设计很简洁，很不错-Verilog I2C TO spi code
rs_204_188----v1.0
- RS 编码和解码Verilog Code, 实现了RS（204,188)的编码和译码；-RS Coding and Decoding Verilog code， implement RS（204,188)
uartverilog
- VERILOG HDL下写的串口驱动程序，经验证可以正常实现串口功能-VERILOG HDL to write serial driver, proven functionality can normally achieve serial
FPGA-BASYS2
- 基于FPGA BASYS2开发板的数字钟，能够实现计时，时间校准，闹钟，整点报时等功能。-Development board based on FPGA BASYS2 digital clock, to achieve timing, time calibration, alarm, hourly chime functions.
FPGA-a-CPLD-kaifajingyan
- 很难得的FPGA与CPLD开发经验，希望对大家有所帮助-Hard to come by FPGA and CPLD development experience