- sms 一个简单的SMS收发程序
- sixiangbujindianjikongzhi 四相步进电机控制系统设计
- Scholarship processing system is developed for a scholarship department of a college. The scholarship department handles the scholarships sanctioned by the government to various students of the colleges. It computerizes all the transactions of scholarship department like issuing of forms
- ChessTest 在一个N*N的棋盘上指定起点坐标及终点坐标
- STCAD.rar stc analog to digital converter simulation
- UCOSII_V2.52 完整版UCOSII
资源列表
statemachine
- 状态机是FPGA系统工程应用中应用较多的工具 能有效实现系统的逻辑功能
eth_top
- 基于逻辑工具的以太网开发，基于逻辑工具的以太网开发-Logic-based Ethernet instrument development, logic-based Ethernet development instrument
freefifo
- 一个同步fifo的测试程序,里面包括fifo的源程序-a test program of sys fifo
EMCRTL
- RTL Code for Design of Extarnal Memory Controller for Accessing Asynchronous SRAM of size 512Kx16
fibonaccicode
- verilog code for fibonacci codes
基于vhdl的四路智能抢答器
- 基于vhdl语言的四路只能抢答器源代码程序
PIE
- PIE DECDODER decotes pulse interval encoding dignal of RFID tags. OUTPUT is serial bits and parallel register (128 width).
adcpwm
- source code is an example of adc and pwm program in atmega 8535. This code will make the microcontroller converts each input of the ADC pin and make it into OCR0 value. This OCR0 value will affect the shape of the generated pwm signal. OC0 pin on POR
bubblesort1024ram
- 快速冒泡排序基于FPGA实现，有测试文件以及设计图，实现1024*32位数序的多数排序，突破传统是的REG类型少数排序，利用RAM，针对RAM中的无序数的地址调换，达到排序目的，仅供学习交流-Rapid bubble sort based on FPGA, there are test documents and design drawings to achieve 1024* 32-digit sequence of the majority of sorting, breaking trad
uart_verilog
- 用verilog编写的标准异步串行通行程序，供大家参考！-Prepared using Verilog standard asynchronous serial passage procedures for your reference!
I2CMaster
- verolog语言编写，功能如标题所示。有问题请联系mxkmxm@126.com-verolog language, functions as the title.
tSinCordic
- 是codic算法实现Sin的浮点C程序，包括定点和浮点程序，已经通过验证.-Sin is codic floating-point algorithm C procedures, including fixed-point and floating-point procedures, has been validated.