资源列表
multi_cpu
- 多周期CPU，mips指令集，实现了部分指令，包含测试程序，verilog-Multi-cycle CPU
decode
- 使用FSM控制，完成32位数据的decode，对DATA_PATH进行监测，Load Return addr from Stack into PC-Using FSM control, complete 32-bit data decode, for DATA_PATH monitoring, Load Return addr from Stack into PC
AD9910
- 基于AD9910的Verilog程序，实现QPSK调制，只要再加少量代码就可实现8PSK调制-Based on Verilog AD9910 procedure, realization of QPSK modulation, just add a small amount of code can achieve 8PSK modulation
weisuijiamadechanshen
- 7位伪随机码序列的产生及分析，附有7位伪随机码序列的Verilog代码-7-random sequence generation and analysis
stack.vhd
- stack for the protocol used to implement into FPGA
tongbu
- 1、搜索出数据流中的帧同步字信号，并给出帧同步标志。 2、系统工作开始后，要连续3次确认帧同步字进入锁定状态后才输出帧同步标志。 3、在锁定状态时，如连续出现3次错误的帧同步字，则帧同步标志输出无效，系统重新进入搜索状态；否则继续输出有效的帧同步标志。 -1, the search for the data stream signal in the frame synchronization word and frame synchronization flag is given.
dct
- 2维DCt源码，可以实现8乘8点数据的2维DCT变换
hufmann
- Huffman coding for JPEG and MPEG files.
systemCFFT_24_16
- c program & vhdl code for fft-c program & vhdl code for fft....
tel
- 电话VHDL，需要的可以看看，多提意见 ，本人不才 只能写这样的-Tel VHDL, can look at the needs and opinions, I can only write this不才
SystemVerilogAssertion
- SystemVerilog Assertion的应用例子。例子均在Synopsys VCS环境下编译通过。-The uploaded files are examples of Systemverilog Assertions. All of the codes are compiled successfully in Synopsys VCS environment.
keyboard
- 实现从键盘输入的vhdl程序，通过按键输入，扫描，键盘去抖动，键盘输出-input from the keyboard