- sms 一个简单的SMS收发程序
- studentscore 学生成绩
- sixiangbujindianjikongzhi 四相步进电机控制系统设计
- Scholarship processing system is developed for a scholarship department of a college. The scholarship department handles the scholarships sanctioned by the government to various students of the colleges. It computerizes all the transactions of scholarship department like issuing of forms
- STCAD.rar stc analog to digital converter simulation
- UCOSII_V2.52 完整版UCOSII
资源列表
hdl
- Verilog code for the PRBS generator, checker and analyzer.-Verilog code for the PRBS generator, checker and analyzer.
I2CMaster
- 一个实现I2C控制接口的控制程序，已经通过仿真验证，并且可以直接调用了-I2C control interface, an implementation of control procedures has been verified by simulation and can be directly called
digital-clock_VHDL
- 使用VHDL实现数字时钟，已在FPGA上验证-use VHDL to build a digital clock, has been validated on FPGA
CIC_bishe
- 测试CIC滤波器的基本性能,并对CIC滤波器做进一步说明！-To test the basic performance of the CIC filter, and the CIC filter to do further!
cuart
- 有关UART的源程序，基于Altera 的 。很好用的，希望对大家有帮助
cuart
- verilog编写的全功能串口-verilog programme of serial port
KEYBOARD
- vhdl语言编写的电子密码锁的键盘程序，本源码复制在word中，请黏贴到MAXPLUS等相应软件下运行-VHDL language electronic locks the keyboard program, the source copy of the word, please stick to the appropriate software, such as MAXPLUS run
ZN-Li-SGKEY(2)
- 一款小家电暖风器双芯片BCD码通信控制部分-Small household electrical appliances dual chip communication
VHDLfiles
- this rar file includes some simple VHDL codes for students.
wishbone_i2c_master
- -- WISHBONE revB2 compiant I2C master core -- -- author: Richard Herveille -- rev. 0.1 based on simple_i2c -- rev. 0.2 april 27th 2001, fixed incomplete sensitivity list on assign_dato process (thanks to Matt Oseman) -- rev. 0.3 may 4th 200
daq_arm_fifo
- 实现FPGA与ARM的通信，数据、地址总线方式-FPGA（xilinx） and the ARM（三星2440） implementation of communications, data and address bus mode
分频器VHDL描述
- 在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。我们知道，在硬件电路设计中时钟信号时非常重要的。-in digital circuits, the need for regular high frequency clock operating frequency for hours, a lower frequency of the clock signal. We know that the hardware circuit design clock signal i