资源列表
using_the_specified_MUX_in_Spartan-3_FPGAs
- 利用 Spartan-3 系列 FPGA 中的专用多路复用器-using_the_specified_MUX_in_Spartan-3_FPGAs
pipeline_lut_multiplier
- pipeline_lut_multiplier, 一个使用查找表实现的流水线乘法器，本程序使用verilog HDL language 语言编写-pipeline_lut_multiplier ，a multiplier based on look up tablets ,and it is programing in verilog language
hdl
- 这是用Verilog HDL写的可调占空比分频控制器，可以挂在Avalon总线上使用-This is written in Verilog HDL with adjustable duty cycle frequency controller, can be hung on the Avalon bus use
Digitalclocksignal
- 数字时钟信号用vhdl语言描述的源代码他光放利用到各个电路中-Vhdl digital clock signal with the source code language to describe his use of light to release all circuits
FPGA
- FPGA开发时编程需要注意的几点，介绍良好的编程序方法与习惯-FPGA development points to note when programming
spartan5
- vhdl program for adc of spsrtan 3e
chapter5
- Verilog HDL的通信系統-Verilog HDL的通信系統
FIFO_V1
- 同步FIFO和异步FIFO程序，希望对大家有用！verilog程序。-Synchronous FIFO and asynchronous FIFO procedures, and hope to be useful! The verilog procedure.
LED_control_VHDL
- 介绍了用VHDL语言编写的程序控制LED 程序简介清晰 还附有仿真波形图
New-Text-Document
- this is souce code for the clock
RS232uart(VHDL)
- 256字节深度的RS232串口程序,共分4个模块,顶层文件\\FIFO程序\\串口收和串口发.经过测试已用于产品.可靠!
sdModel
- SD卡模型设计，可以实现FPGA与SD卡之间的通信。-SD model