资源列表
9.6_PULSE_Level
- 基于Verilog-HDL的硬件电路的实现 9.6 脉冲高电平和低电平持续时间的测量与显示 9.6.1 脉冲高电平和低电平持续时间测量的工作原理 9.6.2 高低电平持续时间测量模块的设计与实现 9.6.3 改进型高低电平持续时间测量模块的设计与实现 9.6.4 begin声明语句的使用方法 9.6.5 initial语句和always语句的使用方法 9.6.6 时标信号发生模块的设计与实现 9.6.7 脉冲高低电平持续
ji_shu_qi
- 在QuartusII软件中用Verilog HDL编写的计数器的源代码-Verilog HDL prepared counter with in QuartusII software source code
16QAM
- 使用verilog编写的16QAM调制解调代码，可用于quartus和ISE，因为不包含FIR，只能用于仿真，不能用于实际通信-Verilog prepared using 16QAM modulation and demodulation code can be used quartus and ISE, because they do not contain FIR, only for simulation and not for actual communication
viterbi
- This a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is w
DE2_TOP
- ps2_keyboard的实现方式，在Altera的DE2板上实现-ps2_keyboard for implementation, implementation in Altera' s DE2 board
serialport
- 用VHDL语言，在FPGA上实现了对RS232串口的控制，能够接收从计算机键盘上输入的字符，并将接收的字符通过串口再发回到计算机。-It is a VHDL program on FPGA controling RS232 ,and it can receive and transmit data normally.
pipe
- verilog编写的流水线模块-Verilog modules prepared by the Pipeline
StopWatch
- 在Modelsim6.3c中编码，与Virtex-II Pro开发板连接实现秒表功能-In Modelsim6.3c encoding, and Virtex-II Pro development board to achieve a stopwatch function
5
- LED控制VHDL程序与仿真，比较简单适合操作-VHDL program LED control and simulation, suitable for operation of relatively simple
dds-dingcengmokuai
- ＦＰＧＡ ＤＤＳ顶层模块 基于FPGA的dds ip核的实现，对于学习通信专业的人应该有些帮助-FPGA DDS 顶层模块
sao-miao
- 按着7654321依次扫描显示，频率为11.0592HZ-Followed by scanning display according to 7654321
hanzi1
- 用VHDL编写的使晶体点阵显示汉字的程序-Written in VHDL, the crystal lattice display Chinese characters of the program