资源列表
chapter6
- 數位調製與解調系統設計 -數位調製與解調系統設計
123
- 再FPGA内部实现数模转换易于增加分辨率，使用-Another FPGA internal digital-analog conversion is easy to achieve increased resolution, the use of
Verilog_add_div_multi_exp
- 使用verilog写的32位浮点数加法模块、浮点数乘法模块、浮点数除法模块、浮点数指数模块。指数模块是综合前面三个例化成泰勒级数求指数，迭代次数（可设置）决定了精度。-Use verilog write 32-bit floating-point addition module, floating-point multiplication module, floating-point division module, the floating point number index module.
12_1
- 用VHDL设计一个分频电路和12归1电路-Design a divider circuit 12 owned by a circuit in VHDL
gray2
- 实现输入一个数字，产生这个位数的所有格雷码-Enter a number of implementation, resulting in the median of all the Gray code
vhdlcode1
- E1 (FIRST ORDER EUROPE TRANSMISSION STANDARD)vhdl
vhdlcode
- E1 (FIRST ORDER EUROPE TRANSMISSION STANDARD)
FPGA_SUM99_VHDL_SOURCE
- 基于FPGA的直接数字合成器的设计与分析的代码程序,代码格式为VHDL-FPGA-based Direct Digital Synthesis Design and Analysis of the code procedures for VHDL code format
modulation-and-demodulation
- 调制与解调系统的FPGA设计实现,包括2-ASK调制和解调,2-FSK调制和解调,2-PSK调制和解调,QPSK调制和解调,PPM调制和解调的verilog源代码。-FPGA design implementation of modulation and demodulation system, including 2-ASK modulation and demodulation, 2-FSK modulation and demodulation, 2-PSK modulation and
seiqinglao
- Optimization class contains several simple sample programs, MIMO OFDM matlab simulation, Includes the modulation, demodulation, signal to noise ratio calculation.
part5
- part 5 lab 2 vhdl altera
fir_lms
- 基于FIR滤波器的LMS自适应算法的FPGA实现-FIR filter based on LMS adaptive algorithm on FPGA