资源列表
state_machine
- 使用8位控制器picoblaze实现状态机的源代码-use eight picoblaze achieve controller state machine source code
gray_counter
- altera官方格雷码计数器的verilog代码和testbench,已测试-altera official Gray code counter verilog code and testbench, have been tested
shifter
- Verilog source code for Shifter logic. Its a simple Shifter to shift a 32 bit variable
series_rxd_timing
- 接收异步串口数据，将数据写到接收fifo中，可设置超时来接收多字节数据，当设置超时时间内未出现数据，ready信号有效，表示接收完整数据包，可从fifo中读取数据。-Receive asynchronous serial data, the data is written to the receiving fifo, you can set the timeout to receive multi-byte data, set the timeout period when the data d
VHDL
- 分频跑马灯数码管示范代码能实现分频跑马灯数码管示范-Crossover Marquee digital control Model Code
RS232
- It s combination logic for UART. Edited in verilog-HDL.
RAM_VHDL_34
- RAM之VHDL描述 RAM之VHDL描述-RAM's VHDL descr iption RAM's VHDL descr iption RAM's VH DL described in VHDL's RAM
Verilog_LCD_Module
- LCd interface to xilinx fpga module
multiply2.rar
- 18bit的booth乘法器 采用booth2编码 Wallace压缩树 以及超前进位结合进位选择的36bit高性能加法器,18bit multipliers used booth2 the booth encoding and Wallace tree compression-ahead into the location choice of high-performance 36bit adder
lcd_1602
- 该代码是用VHDL语言写的，用来控制LCD1602液晶显示器，功能正确。-The code is written in VHDL language to control the LCD1602 LCD display, function correctly.
HardCamera
- The objective of this project is to create a driver for a camera module (we used the OV7620). After taking the image with the camera, the driver will store into the external asynchronous RAM, and then send it to the computer through a serial cable
uart
- 一个简单的UART程序，包括接收，发送，波特率产生-A simple UART program, including receiving, sending, baud rate generation