资源列表
chap7
- 本程序是关于学习VERILOG语言的案例，方便读者快速掌握VERILOG语言的基本语法，操作等-This program is about learning the language of the case VERILOG to allow readers to quickly master the basic syntax of the language VERILOG, operation, etc.
VHDLkeyboard.rar
- 4*4键盘扫描的VHDL程序，可消除抖动，可以帮助大家一下,4* 4 keyboard scan VHDL procedures to eliminate jitter, we can help you
1_instruction_fetching
- Risc processor :- Instruction fetch code
vhdl-多功能电子表
- 这是一个用vhdl编的多功能电子秒表，可以记录几个人的时间，并且可以在跑秒的时候查看记录。。〔原创〕-This is a series with VHDL multifunctional electronic stopwatch, can be recorded by several people, and that they could run in the second examined the records. . [Original]
dianzhen
- FPGA嵌入式开发的源代码，本实例是实现点阵的通信-implementation of pointer array
Buzzer-for-verilog
- 在FPGA上设计实现控制蜂鸣器，程序来自实验开发，验证通过。-Designed and implemented in the FPGA to control the buzzer, the program from experimental development and validation through.
chu_avalon_audio
- avalon sopc audio interface coding
HDB3
- hdb3的编解码实现，用c表述的 实际应用性不强，只为说明原理。-HDB3 codec realize, with the practical application of c expression is not strong, only to illustrate the principle.
EDAclock
- 基于verilog的fpga电子钟设计 有时分秒显示 及闹钟功能-Based on the electric clock verilog FPGA design into four modules that sometimes the alarm clock function determined.
clock_fpga
- 基于VHDL的FPGA设计，设计一款多功能的电子定时器，包括计时跟倒计时。-VHDL-based FPGA design, design a versatile electronic timers, including the timing with the countdown.
zzz
- 智能化人机接口实验，实现开机显示START，输入参数00-99，参数输入个数十个，并存于RAM 50H-99H中。-Intelligent man-machine interface experiments, and boot display START, input parameters 00-99, the number of parameter input ten co-exist in the RAM 50H-99H.
huffmandecoder
- 采用verilog实现反离散余弦变换的程序-The function of realizating Inverse discrete cosine transform