资源列表
dso
- 基于fpga的简易数字存储示波器设计，包含采样，检测触发，波形存储等模块功能-Fpga-based design of simple digital storage oscilloscope, including sampling, testing the trigger, waveform storage module functions
8. FILTER
- DIGITAL FILTER GUI matlab
VHDL_BASIC_CONCEPT
- VHDL 基本概念，有助于帮助初学者快速理解VHDL基本概念和内容，快速掌握。-VHDL BASIC CONCEPT,which discribes the basic concept of the vhdl design.
VHDL3
- vhdl进行高层次设计,对于做工程的很有。源程序还是有介绍.
cordic
- altera cordic ip core, 包含文档，完整设计，以及测试向量-altera coedic ip core, including the document, whole design, and the testbench.
test2
- 1、用 VHDL 语言的不同语句分别描述任务选择器，并通过编译仿真比较不同语 句描述的区别。 2、通过仿真下载并通过硬件验证实验结果。-1, different statements are described in VHDL language task selector, and distinguished by comparing different statements compiled simulation described. 2, and verify the results
Altera
- “Altera杯”第五届全国研究生电子设计竞赛样板-" Altera Cup" of the Fifth National Graduate Electronic Design Competition model
ddr-sdram
- It is complete document for DDR SD RAM program in verilog hdl
colour_light
- 一个圣诞彩灯控制芯片的vrilog源代码，可以综合，经过FPGA验证，产生四路输出，控制四路彩灯，有跑马闪，星闪等多种功能
RS
- RS编码器的VHDL源程序,程序有点大，不过能用。-RS encoder VHDL source code, program a little big, but can be used.
DDR3_quartus14.1_tutorial
- quartus14.1 DDR3仿真教程，带有实际测试例子，可以在项目中参考-ddr3 sim tutorial，tools quartus14.1 and modelsim10.1
Tx_state
- 应用于实时以太网通信，通过高速FIFO实现异步时钟域通信，通过状态机实现FIFO操作，实现与物理层芯片通信。-Used in real-time Ethernet communication, asynchronous clock domain communication speed FIFO FIFO operation state machine, with the physical layer chip communication.