资源列表
FPGA_Design_experience
- 讲解了在FPGA中时序设计时应该注意的问题，并分享了设计经验-On timing in the FPGA design should pay attention to the issue and to share the experience of the design
my_and
- 此实验例程适用于Actel Flash架构的ProASIC3/E系列FPGA，适合于FPGA及Verilog HDL的初学者，配套EasyFPGA030开发套件。-Routine application of this experiment in the Actel Flash architecture ProASIC3/E series FPGA, fit in the FPGA and Verilog HDL for beginners and supporting development
VHDL
- 数字系统设计中的全加器、10进制计数器、2-4译码器、摩尔状态机、2-1路选择器的源代码
1111
- verilog编写的计数显示模块，应用了文件关联，可以自由调用-Verilog write count display module, the application of the file associations, free calls
system 完成远程通信的整体任务
- Verilog，QuartusII可正确运行，可下载到FPGA上，完成远程通信的整体任务，PC发数据，键盘输入运算符与运算数计算将结果显示在数码管上并返回给PC机，需异步串口调试软件-Verilog, QuartusII run correctly, can be downloaded to the FPGA, to complete the overall task of remote communication, PC send data, keyboard operators and op
synplify_pro-text
- 介绍了synplify pro的使用方法，好不容易找到的，欢迎下载，希望与大家共享。-introuducing the text of synplify pro,it is fit for learning the application of the soft
parall_ad_da
- Verilog初学者实验程序。已在quartus下测试成功。-Verilog beginners experimental procedures. Been in quartus under test success.
nexys4vgamouseoverlay
- Demo code for mouse, nexys4 made by digilent
cpu
- 很重要的cpu hdl，实现了各种功能,对学习很有帮助的-Very important source site to achieve a variety of functions, useful for learning
vhdlcpu
- 很重要的cpu hdl，实现了各种功能,对学习很有帮助的-Very important source site to achieve a variety of functions, useful for learning
Pld-based-VGA-display
- 基于pld和Verilog语言的VGA显示，内容为雨后彩虹。-Pld-based VGA display
chunchuqidesheji
- 在计算机系统中，一般都提供一定数量的存储器。在用FPGA实现的系统中，除可以使用FPGA本身提供的存储器资源外，还可以使用FPGA的外部扩充存储器。本实验要求设计一个32×8 RAM，如下图所示，它包含5位地址、8位数据口和一个写控制端口。-In the computer system, generally provide a certain amount of memory. FPGA implementation of the system in use, unless you can us