资源列表
ADC12-sampling-experiment
- DC1工作时钟为14Mhz，使用ADC1的通道8来连续转换，并使用DMA来传输转换数据，并在TFT 上实时显示转换数据（显示的是直接读出的ADC规则数据寄存器中的值，即为低12位）-DC1 work for 14 Mhz clock, use ADC1 channel 8 to continuous conversion, and use the DMA to convert data transmission, and in the TFT To convert data on rea
Software-Defined-Radio-for-OFDM-Transceivers
- Software-Defined Radio for OFDM Transceivers
nova_latest
- h.264完整的解码器，用verilog实现，属于opencores-h.264 full decoder, implemented by verilog, one of opencores
led_8_8_moving
- VHDL 8*8双色点阵，滑动显示“西安电子科技大学”-VHDL 8* 8-color dot matrix, slide shows XiDian University "
hw5
- 32-bit adder CLA, CSKA adder
FClock
- clock code using VHDL
FFT
- fft implementation in fpga using vhdl xilinx
DDR（双速率）SDRAM控制器参考设计verilog代码
- DDR SDRAM reference design documentation
ECP3SerDesEyeDemo
- ecp3 serdes程序用来操作fpgaserdes-ecp3 Serdes procedures used to operate fpgaserdes
zs
- 基于fpga的数字频率计，verilog编写，可修改闸门宽度0.1s/1s/10s，可测频率1hz~1mhz，包含整个工程，内部分频模块为了仿真方便改小了，后面注释为50mhz晶振下的分频值，可根据需要自行修改-Fpga-based digital frequency meter, verilog prepared to modify the gate width 0.1s/1s/10s, measurable frequency 1hz ~ 1mhz, contains the entire
very-good-ok-ref-ddr-sdram-verilog
- Sdr SDRAM控制器参考设计,很好的-Sdr SDRAM controller reference design, very good
mylcd
- Xilinx中lcd显示屏两行显示+启动程序+滚动-Xilinx lcd display