资源列表
ref-sdr-sdram-verilog
- sdram的verilog 建模参考设计，希望有所帮助-sdram and verilog implent
AWGN_VerilogDesign-master
- 加性高斯白噪声生成的VERILOG实现，包含所有的testbench文件。可直接使用-Additive white gaussian noise generated VERILOG realized, including all testbench files. Can be used directly
EasyFPGA060_Routine_Adder
- EasyFPGA060 加法器实验及文档-EasyFPGA060 adder test and documentation
ddr2_demo
- lattice 操作DDR2控制器verilog源代码-the verilog source code of ddr2 control of lattice
pinlvji
- 六位数字频率计的设计程序，包括管脚的分配，分频设计，显示设计-Six digital frequency meter design process，Pin assignment, crossover design, display design
DDRSDRAM_VHDL
- 内附doc是DDR SDRAM 参考设计文档；model包含SDRAM VHDL的模型；simulation包含VHDL测试平台、modelsim工程文、设计 库函数；source包含vhdl源文件；synthesis包含工程的综合文件。-Enclosing the doc is a DDR SDRAM reference design documentation model contains SDRAM VHDL model simulation with VHDL test benc
vhdlexperiences
- 计数器、频率计、优先编码器、数码管扫描电路、数据选择器-Counter, frequency meter, priority encoder, digital tube scanning circuits, data selector
FPGAyinpin
- 基于FPGA的VHDL编程实现各种音频信号，采用的是周立功公司的fusion_startkit开发板。
alu
- desein a simble 32 bit alu
spare
- 最简单的4位2进制比较器，可下载到实验箱上，已经过硬件验证-2 simple binary comparator 4 can be downloaded to test me on hardware verification has been
Analog-Circuit-4Ed-Exercise-Answer-
- 模拟电子技术基础课后练习题答案，童诗白第四版-Analog Circuit 4Ed Exercise Answer
fifo_FPGA
- 68013 FIFO 接口程序，USB开发、VHDL开发(68013 FIFO USB VHDL FPGA)