资源列表
ddfs
- 直接数字频率合成器，整个工程文件都在，仿真也有，直接就能用。-Direct digital frequency synthesizer, the entire project file are in the simulation is also directly be able to use.
interface
- 单片机和CPLD的接口实现，能够实现数据的读写。-MCU and CPLD' s interface can read and write data.
T_uart
- CPLD发送模块的实现代码,设计按键检测模块，并将键值通过构造的UART发送模块发送到串口调试工具中查看。--发送格式：1位起始位+8位数据位+1位停止位=10位-CPLD implementation of the code to send the module to design key detection module, and key by constructing the UART to send the module to send to the serial port debugg
Altera_FPGA_Config_Handbook
- FPGA存储器的配置原则指导手册,包含所有类型的Altera公司FPGA芯片-FPGA configuration memory principles to guide manual, including all types of Altera' s FPGA chips
FPGA2
- FPGA技巧篇，系统的介绍了FPGA在应用当中的一些技巧，以及对应用中会遇到的问题进行了解答。-FPGA techniques articles, systematic introduction of the FPGA in the application of some of these techniques, as well as the application will encounter problems of answers.
FPGA1
- FPGA基础学习，系统的介绍了FPGA，特别适合初学者。-FPGA-based learning, a systematic introduction of the FPGA, is particularly suitable for beginners.
NewFolder
- these are the codes written in verilog which are for a dual elevator design
VHDL_32bit_timer
- VHDL写的32位计数，两个四位共阳数码管输出 串口输出+数码管显示的计时器程序 每次停止后串口输出。-VHDL to write 32-bit count, a total of two 4-yang control output serial digital output+ digital tube displays each stopped the timer program serial output.
VHDL2
- Here i have uploaded many other VHDL codes.
DE2_70_NIOS_14_ssram
- Altera公司DE-70开发板中16位SDRAM的32位用法，纯硬件实现哦-Altera DE-70 16MX16SDRAM =>32bits
clock
- verilog HDL 编写的时钟分频器-prepared by the clock divider verilog HDL