资源列表
mt48lc4m32b2.v
- SDRAM VHDL/Verilog simulation model
FIFO.tar
- FIFO design VHDL/Verilog design
dpmem2clk.tar
- Dual port memory VHDL/Verilog design
spmem.tar
- Sinlge port RAM VHDL/Verilog design
shukongdianyabiao
- 使用51单片机以及键盘液晶作为人机互动，输入你想输入的电压值，端口就输出相应的二进制数-51 MCU and LCD using the keyboard as a human-computer interaction, input you want to input voltage value, the port on the output of the corresponding binary number
lab4
- vhdl uart lab ENTITY uart IS PORT ( SIGNAL clock,reset : IN STD_LOGIC SIGNAL sdatain : IN STD_LOGIC SIGNAL oready, sdataout : INOUT STD_LOGIC SIGNAL iready : INOUT STD_LOGIC SIGNAL charin : INOUT STD_L
v
- verilog code for a synthesizer based on Terasic s Multimedia development board. (MTDB) and Altera FPGA.
upload
- 包含三个Project 两个开发板为altera FPGA，另一个为51板。功能：TFT 开发。 包含点亮测试，及OTP等。-Project 2 consists of three development boards for altera FPGA, the other for 51 boards. Function: TFT development. Contains the light test, and the OTP and so on.
fre500000
- 等精度数字频率计的Verilog源码，从上到下的设计思路，分为6个模块。上过Altera公司的FPGA板。 供大家参考，希望大家不要照抄！-Such as precision digital frequency meter Verilog source code, from top to bottom of design ideas, divided into six modules. Been to Altera' s FPGA boards. For your reference, h
FINAL_OUT.VHD
- this is a vhdl program to test your LCD
time
- 电子钟实现 包含数字跑表 万年历 设置三个闹钟 时间，日期调整-Clock to achieve with digital stopwatch calendar set three alarm time, date, adjust
graphicallcd_latest.tar
- grapic automatically delete the directory of debug and directory of debug