资源列表
DSP_DesignFlow_User_Guide
- DSP Builder开发全部流程介绍,从事FPGA开发与设计的人员使用-DSP Builder development of all the processes introduced in FPGA development and design staff to use
SOPC_Builder_Memory_Subsystem_Development_Walkthro
- SOPC Builder 嵌入式系统设计中存储器配置手册-SOPC Builder design of embedded systems memory configurations Handbook
Cyclone_Series_Device_Thermal_Resistance
- cyclone系列FPGA的串行设备阻抗匹配设计指南-cyclone series FPGA Design Guide impedance matching of serial devices
Altera_Device_Package_Information
- Altera 全部型号的FPGA及CPLD的配置指南,做PCB和FPGA开发人员参考较好-Altera all model FPGA and CPLD configuration guide, PCB and FPGA developer to do a better reference
NIOSII_Other_Tools
- NIOS II研究开发者使用手册,其中讲述了一些实用工具的说明。-NIOS II research and development to use the manual, which describes some useful tools for descr iption.
alu_32_bit
- 一个Verilog语言写的３２位ＡＬＵ的源码。-A language written in Verilog source code for a 32-bit ALU.
SIG_1KHz
- 任意移相方波信号产生的VHDL代码。输入任意一个的相位偏移值就都能产生与参考方波有指定相位差的同频信号。-Square-wave signal of arbitrary phase shift generated by VHDL code. Enter any one of the phase offset can be generated on a designated phase with the reference square wave signal the same frequency
viterbidecoder
- viterbi译码器的Verilog实现,(3,1,7)零尾卷积码-viterbi decoder implementation by verilog HDL （3，1，7）zero tail conventional code
buzzer
- 用Verilog HDL写得能给蜂鸣器输出‘哆、唻、米、发、嗦、啦、稀、哆（高音）’声调的程序-Buzzer to give written using Verilog HDL output ' duo, Lai ... ...' tone of the program
ps2_DE1_HEX
- Display Scancode of PS2 on DE1 board !
PetervrlK_verilog
- Verilog Introduction , a general summary of syntax and structure of Verilog language !
oc_i2c_master_bit_ctrl_v92
- I2C IP for Quartus V9.0 sp2, can used in SOPC builder.