资源列表
B2BCD
- 基于VHDL的二进制转BCD码，简单高效，占用资源少，是国外一本最新书籍提倡的一种写法。-Binary switch based on VHDL BCD code, a simple and efficient method of resource usage, less is foreign advocates a kind of writing a new book.
yibufifo
- 讲诉fifo配置设计中，一些程序例程，仅供参考，相互学习一下-Recounts fifo configuration design, some routine, for reference, to learn about each other
VGA
- 在分辨率为800 * 600的VGA显示器的行和场各显示一个边长为100的正方形方块移动。 -In a resolution of 800* 600 VGA display of line and field shows a side length is 100 square square of mobile.
VGA_move
- 在分辨率为800*600的VGA显示器的行和场各显示一个边长为100的正方形方块的移动。-In a resolution of 800* 600 VGA display line and field each shows a side length is 100 square square of mobile.
LCD_counter
- xilinx spartan3E 开发板上LCD显示屏驱动，并显示周期为一分钟的计数器。-Xilinx spartan3E development board on the LCD display drive, and display the cycle counter for a minute.
rotation_adjust
- xilinx spartan3E开发板上旋转按钮的驱动，利用旋钮旋转控制LED灯的亮暗程度，从灭到亮有10种不同的亮度。-Xilinx spartan3E development board rotate button on the drive, using the knob control LED lamp brightness level, there are 10 kinds of different from out to bright brightness.
Digitron_driver
- 分模块描述的8位数码管驱动，在上面静态显示12345678.-Points module describes eight digital tube driver, in static display above 12345678.
FIFO
- 用VHDL语言写的FIFO IDT7205驱动程序。时序仿真无误！-VHDL language used to write the FIFO IDT7205 driver. Timing simulation is correct!
Verilog_prj
- 特权同学的CPLD学习版 Verilog和VHDL代码。含有仿真文件。-Learning Edition privileged students CPLD Verilog and VHDL code. Contains simulation files.
CLK_Detector-
- 时钟（2m、34m、45m、58m、77m、155m)检测-CLOCK INCLUDING(2m、34m、45m、58m、77m、155m)DETECT
GMSK
- GMSK调制解调、M序列生成、眼图模拟、相位路径查表。-GMSK modulation and demodulation, M sequence generator, eye diagram simulation phase path lookup.
Lab5.5_Led_FPGA
- 使用verilog在fpga开发板实现流水灯，包括整个工程文件-This code is used for early learners to study verilog。