资源列表
xapp341_verilog
- Xlink应用例子关于UART的Verilog实现的源代码-Xlink application examples about UART Verilog realization of the source code
detector
- 本程序实现8位序列检测的功能-the program eight Sequence Detection functions.
vhdl
- vhdl YCBCR2RGB 111 11的转换-vhdl YCBCR2RGB
fudian_sub
- 实现32位浮点减法器，具体结合加法器和乘法器来实现快速傅里叶变换。-use VHDL to finish the sub device.
vhdl_transfer_of_data_types
- VHDL, the transfer of data types
vertosysc
- verilog转换为systemc代码,用于RTL到系统建模-verilog to systemc
uart_0
- 异步串行通信Uart接口设计，Verilog HDL程序，嵌入式必备哦
Flash_ctrl_vhdl_tb
- ＶＨＤＬ编写的flash控制器源代码.包含testbench。-Prepared by flash controller VHDL source code. Contains testbench.
all-pole_filters_latest.tar
- all pole filter for dsp
dds_ise7.1_su
- 用Verilog语言实现信号发生器，包括AM，FM,PM，ASK,PSK,FSK调制。-using Verilog language signal generator, including AM, FM, PM, ASK, PSK, FSK modulation.
make-NIOS-elf-FPGA-sof_into-jic
- 将FPGA的硬件配置程序和NIOS产生的软件程序合并，方便下载。-The FPGA hardware configuration program and NIOS software program produced by merging, easy download.
all-pole_filters_latest.tar
- All polar vector and its vhdl code with testbench