资源列表
spitoi2s3
- spi转i2s的verilog程序，fpga是总模块，spi和i2s是子模块，shiftreg是转换-spi transfer i2s the verilog program, fpga is the total module, spi, and i2s is the sub-module, shiftreg is to convert
gold_code_vhd_217
- Gold Code Generators in Virtex Devices
spwm_gen
- 正弦脉宽调制SPWM波的产生VHDL代码与相关IP核产生与说明，-Nuclear generation and descr iption of the sinusoidal pulse width modulation SPWM wave generated VHDL code and related IP
u-uart
- 一个可综合的串并转换接口verilog源代码-a comprehensive series of conversion and interface Verilog source code
ANS
- 按 SW3 / SW4 / SW5 开始抢答，抢答后数码管显示抢答结果，倒计时停止。-Press SW3/SW4/SW5 start Responder, Responder Responder results after the digital display, the countdown stops.
sanjiaobo
- 三角波生成 和 正弦的 vhdl的语言编写-The preparation of the triangle wave generation and sinusoidal VHDL language
diglab3
- lcd test on the altera de2 board with switches and leds
VHDLverilogshirenqiangdaqi
- 用VHDL和verilog实现的四人抢答器-using VHDL and verilog realization of four Responder
ps2_mouse
- ps2 mouse controller
LinPF_RLS
- VHDL code for linear prediction filter based on RLS (recursive least square). Filter order is set to 4, bit precision set to 12 bits for input and output. Signals are complex signals.
clock
- 数字时钟的Verilog代码，该实验经本人测试，正确无误。-Digital clock Verilog code, the experiment after my test, correct.
Mulitiplier_Hardwired_Control
- The code is a multiplier that use the structure of datapath and hardwired control. It can be implemented on the Atlys board.