资源列表
mxuliematlab
- m序列在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-m sequence in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
boundaryscan1949.7
- 边界扫描程序调试案例，用于电路板自动测试中-Case of boundary-scan debugging, automated test for circuit boards
cpld-usb
- usb-fpga通讯，从cpld到usb协议芯片slave fifo的通讯过程指导。-The usb-FPGA communication from the CPLD to usb protocol chip slave FIFO communication process guidance.
The-FSK-digital-demodulato
- 基于FPGA的FSK数字解调器研究与实现.FSK解调器；FPGA器件；VHDL语言；Matlab；QuartusⅡ仿真-The FSK digital demodulator research and implementation based on FPGA
post_norm_fmul2
- Post_norm_fmul2 vhdl code
Call-by-Value
- Describe a syntax of "Call by value"
d-flip
- 同步复位的D 触发器，该触发器有一个数据输入端D，时钟输入端CLK，清 零输入端CLR，数据输出端Q。CLR为1时，触发器复位-Synchronous reset D flip-flop, the flip-flop has a data input D, the clock input CLK, clear input CLR, the data output Q. CLR 1, the trigger reset
timer_netlist
- netlist of an alarm clock circuit
source
- IO转UART的数据收发控制和收发数据代码，中文注视，能够清楚了解代码含义-IO UART data transceiver control and send and receive data code, Chinese gaze, knowing code meaning
XillinxFor_CKJH
- 北京百科融创科技有限公司编写的DSP与FPGA接口通信程序源码-Financial Innovation Technology Co., Ltd. Beijing encyclopedia written DSP and FPGA Interface Communication Source
hdl
- ACTEL FPGA 交通灯，Verilog描述-ACTEL FPGA traffic lights, Verilog descr iption
Traffic-Controller
- 本代码为基于Spartan6的verilog交通控制灯代码，在ISE软件中仿真成功。-The code for the verilog code Spartan6 traffic control lights on in the ISE software emulation success.