资源列表
chap3
- Verilog源代码一共135例chap3-chap12，初学必备-Verilog source code for a total of 135 cases of chap3-chap12, beginner necessary
dcmotor
- PID dc motor control on Nexys 2 FPGA
pe
- 卷积神经网络当中的卷积模块，包括有测试程序，用硬件实现5*150的整列卷积-Convolutional neural network convolution module, including a test program, with hardware to achieve 5* 150 integer convolution
PLL.ZIP
- the code specifies how to model a pll using vhdl code
同有SPI接口的器件进行通信对SPI接口器件的读写控制vhdl源程序
- vhdl实现spi可以同有SPI接口的器件进行通信对SPI接口器件的读写控制vhdl源程序，fpga cpld-vhdl spi can achieve devices with a SPI interface to communicate with devices on the SPI interface to read and write vhdl source code control
multi
- vhdl add code and sub code. also some more codings ae th-vhdl add code and sub code. also some more codings ae thee
UART
- verilogHDL语言实现的uart模块，内部包含波特率生成、uart收、uart发三个子模块，支持配置常规波特率、数据位、结束位和校验位，输入工作时钟125M，时钟不一样时需要修改波特率生成的代码-verilogHDL language of uart module contains an internal baud rate generator, uart receive, uart made three sub-module, configured to support conventi
trellis_verlog
- ATSC发送端部分，ATSC标准特有的TCM编码，共6个文件，包含tb文件，已通过仿真，没有问题，verilog代码-ATSC transmitter, the ATSC standard TCM unique coding, a total of six documents, tb-contained documents, had passed through simulation, no problem, verilog code
LF_therapy
- low frequency therapy system control VHDL code
control
- 用VHDL语言编写的一个控制程序，主要功能是输入码同步，输出字和帧信号-VHDL language using a control program, the main function is to input code synchronization, and frame signals output word
Arbi
- this the code for arbiters used for master and slave foermat-this is the code for arbiters used for master and slave foermat
asjan
- Independent component analysis for image processing, Weighted acceleration, Classic GLCM texture calculation method.