资源列表
FPGA_experiment_new
- 关于ＦＰＧＡ开发的实验例程，ｖｅｒｉｌｏｇ相关-Experiments on the FPGA development routines, verilog-related
fir_Verilog
- 用Verilog编写的fir滤波器程序！-Verilog prepared using the procedure fir filter!
source
- Single Channel LVDS Tx - Source Code-Single Channel LVDS Tx- Source Code
FIR
- ＦＰＧＡ实现数字滤波器，基于硬件描述语言ＶＥＲＩＬＯＧ ＨＤＬ，顶层文件ＦＩＲ．Ｖ
rotW
- Rotating Wheel is a simple digital circuit which makes use of a Seven Segment Display (SSD). It causes a continuous clockwise/anticlockwise movement of the SSD segments. Also, the circulatory movements are made more realistic by providing momentary o
AdcClock
- Device: Virtex-6 -- Author: Marc Defossez -- Entity Name: AdcClock -- Purpose: High-speed local clock control for an interface between a FPGA and a -- Texas Instruments ADC. -- Tools: ISE - XST -- Limitations: none -- -- Revis
MUTICOUNT
- 一个关于计数器的VHDL实例，对于VHDL语言的学习者很有帮助。-VHDL on the counter example, the VHDL language learners helpful.
sirenqiangdaqi
- 设计一个4人参加的智力竞赛抢答计时器。电路具有回答问题时间控制功能。-4 participants to design a quiz answer in timer. Time control circuit has functions to answer questions.
81404600digitalclock
- 很强大的工具 希望大家可以喜欢 在生活中的应用-Very powerful tool for hope that we can enjoy the application in life
digitalclock
- 这是一个数字钟的VHDL实现.采用八段数码管显示！ --可调闹铃，可校时。
can
- can module for vehicle automation
vga_3bits
- 3位宽的vga接口的verilog代码，调试通过，在FPGA上可以综合。-3-bit wide vga interface verilog code, debugging through, can be integrated on the FPGA.