资源列表
rgstr
- ADC12D800 source code
dcm100
- ADC12D800 source code
an489
- 用于MAXII系列EPM240T100 CPLD中UMF使用的例程及说明文档-Routines and documentation for MAXII series CPLD used in UMF
fir16.v
- 16阶FIR滤波器设计的verilog代码-Verilog 16-order FIR filter
fir48
- 48阶FIR滤波器的verilog，包含测试文件-48-order FIR filter verilog, including test paper
DE1_D5M
- // --- --- --- --- --- --- --- --- --- --- --- -- // Copyright (c) 2007 by Terasic Technologies Inc. // -------------------------------------------------------------------- // // Permission: // // Terasic grants permission to use and mod
da2c
- VHDL硬件描述语言实现DA转化-In quurtus call half adder to achieve 16-bit serial adder
pipeline_mips_simulation_using_xilinx
- This project is a pipeline simulator using xilinx. All of fetch, decode, execute and write back stages was implemented. That is a nice project for computer architecture course in computer engineering. Good Luck ) -This project is a pipeline simul
digital_timer
- 能够使用4个按键，实现调时。一个选择，一个取消，一个加时间，一个减时间。-Four keys to use to achieve the transfer. A selection, a cancel an add time, a reduced time.
liushuideng
- verilog做的流水灯，分频器做半秒的tc，流水灯每半秒流动一次 -verilog do water lights, dividers do half a second tc, light water flow once every half-second
0--9999
- 0--9999，计数数码管点亮，流水灯多种特别流动，流动的间隔时间为1s-0- 9999 count digital tube lights, a variety of special light water flow
22
- 2x2按键四位数码管输入四个数字，可以同时显示4个数字，并可以清零，与此同时，防抖动-2x2 button four digital input four digits, you can simultaneously display four digits, and can be cleared at the same time, anti-shake