资源列表
Verilog
- 一本简单的详细的介绍verilog语法的知识手册-this is a samll book which have introduce the verilog very detail
FPGA
- Learnado Spectrum for simulation software
WAVE6000
- 基于VHDL语言设计一个全双工UART电路，主要模块：波特率模块、数据发送模块、数据接收模块。-VHDL language design based on a full-duplex UART circuit, the main modules: module baud rate, data transmission module, the data receiver module.
Altera_Verilog_Coding_Style_Proposal_final
- Altera的Verilog 代码规范，讲解的还可以-Altera' s Verilog code specifications, explanations can also be
counter
- This a simple Counter -This is a simple Counter
vc
- virtul channel 虚拟通道 用于改善noc的死锁效应-virtul channel virtual channel used to improve the effect of noc Deadlock
SDRAMController
- xilinx公司SDRAM的参考设计,调试成功-xilinx' s SDRAM reference design, debug successful
jiaot
- 一个很简单的交通灯控制器，容易理解，在EP1C3T140C8上跑过-A very simple traffic light controller, easy to understand, in the EP1C3T140C8 ran
mb
- 简单秒表(1分钟)，希望对初学者有帮助，VHDL-Simple stopwatch (1 minute), want to be helpful for beginners, VHDL
rom
- 一个ROM读数据代码，简单，一目了然，一起学习-A ROM read data code, simple, clear, along with learning
FPALU_TestBench
- floating point unit
Anne
- write "AnnE" with 7 segment display using vhdl code at spartan 3e